Tonight in San Jose, Ian Buck — the NVIDIA vice president who built CUDA two decades ago and in doing so handed every deep-learning researcher on earth a practical on-ramp — will tell data-center architects how to build an AI factory that spans continents. His keynote at OCP 2026, scheduled for 5:45 PM PT at the San Jose McEnery Convention Center, is expected to center on four platform pillars NVIDIA has been assembling since January: the Vera Rubin NVL72 rack, the Vera CPU, the Spectrum-XGS scale-across network, and the DSX factory management suite. Of the four, Spectrum-XGS carries the largest structural implication — one the industry is only beginning to price in: for the first time, geography stops being an AI factory constraint.

The summit, now sold out at 7,000 to 9,000 attendees and running October 12–15, is the premier venue for the open hardware ecosystem that now supplies most of the world’s hyperscale compute. Buck’s session — formally titled “AI Factories at Scale: Advancing Open Infrastructure for Agentic AI” — is one of more than 22 conference sessions the event will host across four days.

Ian Buck: Architecture’s Constants Change With CUDA, and Now With Spectrum-XGS

Ian Buck joined NVIDIA in 2004 after completing a PhD at Stanford, where his work on the Brook streaming language — described in Buck’s Stanford dissertation on streaming — laid the conceptual groundwork for general-purpose GPU computing. As NVIDIA’s vice president of Hyperscale and HPC, he has led the company’s GPU computing strategy for more than twenty years, overseeing the period in which the NVIDIA CUDA unified computing platform became the de facto programming model for AI research worldwide.

That history matters for tonight’s audience of open-hardware engineers. When Buck speaks about AI factory architecture, he is drawing on the same instinct that drove the creation of CUDA in 2007: that the constraint everyone accepts as fixed — in 2007, the GPU’s inaccessibility to programmers; in 2026, the data center’s geographic boundedness — is an engineering problem, not a physical law.

Buck holds a BS from Princeton as well as his Stanford doctorate, and has been central to NVIDIA’s technical direction through the GPU computing era, the deep-learning era, and now the agentic AI era, as detailed in his Ian Buck official NVIDIA biography. His keynote will be the first major industry-facing presentation of all four architecture pillars together, with production data now behind at least one of them.

Spectrum-XGS: NVIDIA’s Answer to the Geography Problem

The core claim NVIDIA will advance tonight is that Spectrum-XGS, first detailed at Hot Chips in August 2025, adds a “scale-across” capability to its Ethernet networking portfolio that did not previously exist. Where conventional data-center networking literature describes three tiers — scale-up (within a server), scale-out (across servers in one facility), and the WAN link between facilities — the NVIDIA Spectrum-XGS Hot Chips announcement proposes a Spectrum-XGS scale-across fourth layer that treats geographically separated clusters as a single logical fabric.

That claim changes the economics of where AI factories can be built. Until Spectrum-XGS, a single large training run had to live inside one facility: network latency and bandwidth constraints between sites made distributed training impractical at rack scale. If Spectrum-XGS delivers on its architectural promises, an operator will be able to spread a single training job across facilities in, say, Austin and Stockholm without the job experiencing those sites as separate. The practical result is that operators will no longer need to find a single campus capable of housing every GPU a frontier model requires — they will be able to build modularly, in locations chosen for power cost, land availability, or regulatory environment, and stitch them together through Spectrum-XGS fabric.

CoreWeave Oracle Spectrum-XGS deployment has already been announced, with both companies among the first operators named as Spectrum-XGS adopters.

How Does Spectrum-XGS Actually Work?

Three engineering mechanisms enable Spectrum-XGS’s scale-across capability.

First, co-packaged optics switch technology: rather than using pluggable transceivers in standard form factors such as SFP or QSFP, co-packaged optics (CPO) integrates optical components directly into the switch package. The result is higher bandwidth density and lower power per bit than pluggable optics can achieve — critical when linking facilities across long-haul fiber, where every watt of transceiver overhead limits throughput.

Second, distance-aware congestion control algorithms: Spectrum-XGS carries intelligence about the latency profile of each link in the fabric and adjusts flow control in response to that profile. Standard congestion control algorithms assume uniform latency — a reasonable assumption inside one building, an incorrect one across cities. Spectrum-XGS treats heterogeneous latency as an input to the scheduler, not a failure mode to work around.

Third, Spectrum-XGS end-to-end fabric telemetry: the platform maintains a real-time view of the full fabric, from NIC to switch to optical link. This visibility is what allows the scale-across scheduler to treat geographically distributed GPU clusters as one system rather than two systems with a pipe between them.

Vera Rubin NVL72: The Rack That Already Has Production Numbers

NVIDIA announced the Vera Rubin NVL72 CES 2026 announcement at CES on January 5, 2026. The platform packs 72 Rubin GPUs and 36 Vera CPUs into a single rack, connected by sixth-generation NVLink at 260 TB/s within the rack. The NVLink 6 rack-level bandwidth spec of 260 TB/s — the aggregate bandwidth within one rack — eliminates the interconnect as the bottleneck inside the rack so the GPUs can be fed at the rates their compute density demands. The Rubin GPU NVFP4 inference specs show each Rubin GPU delivering 50 petaFLOPS of NVFP4 inference throughput and 35 petaFLOPS of training throughput, backed by 288 GB of HBM4 memory per GPU at 22 TB/s memory bandwidth.

Those specifications became production numbers on September 30, 2026, when CoreWeave Vera Rubin production availability was announced, with Cognition — the company behind the Devin AI coding agent — as the first production customer. Cognition reported a Cognition 4.8x token throughput benchmark compared with the GB200 NVL72 it replaced. On DeepSeek R1 inference workloads, NVIDIA projects a 10x throughput per megawatt claim compared with prior-generation hardware — a figure that, if it holds at scale, changes the cost structure of inference providers materially.

The 260 TB/s intra-rack NVLink 6 bandwidth — versus the approximately 64 GB/s ceiling of PCIe 5.0 — is the architectural feature that makes the NVL72’s GPU count practical: it eliminates the interconnect as the bottleneck inside the rack so the GPUs can be fed at the rates their compute density demands.

Vera CPU: Why NVIDIA Built Its Own Processor to Eliminate the Agentic AI Bottleneck

The Vera CPU custom Olympus core design inside the NVL72 is not a licensing agreement or a procurement choice — it is a ground-up NVIDIA design built around a specific observed problem in agentic AI workloads.

The problem: in agentic inference — where a model generates a chain of reasoning steps rather than a single output — roughly 75 percent of compute time is spent in the decode phase, during which the CPU can become a throughput bottleneck if its bandwidth to the GPU is insufficient. Standard x86 CPUs communicate with GPUs over PCIe 5.0, which maxes out at approximately 64 GB/s per x16 slot.

The Vera CPU, built on 88 custom Olympus cores, connects to Rubin GPUs via Vera CPU NVLink-C2C bandwidth spec at 1.8 TB/s — representing a 28x improvement in CPU-to-GPU bandwidth over PCIe 5.0 x16. Beyond bandwidth, Vera’s multi-threading architecture assigns each thread full core bandwidth rather than sharing it across simultaneous threads the way conventional SMT designs do — meaning agents that launch parallel reasoning chains do not starve each other for memory bandwidth. In NVIDIA’s benchmarks, the result is 1.8x faster agent task completion compared with x86-based configurations.

DSX: Software That Turns a Building Into an AI Factory Before the Hardware Arrives

NVIDIA made the NVIDIA DSX GTC Taipei announcement at GTC Taipei on May 31, 2026. DSX is a factory management stack with four components, each targeting a different operational constraint in the path from empty building to producing AI cluster.

DSX OS open-source operations software is an open-source platform for AI factory operations management, giving operators and OEMs a common instrumentation and orchestration layer. The DSX MaxLPS 45°C liquid cooling spec enables sustained 45°C coolant inlet temperatures, raising the GPU density achievable within a given power budget by approximately DSX MaxLPS 40 percent GPU density compared with traditional cooling approaches. That 40-percent improvement compounds: more GPUs per rack, less cooling overhead per GPU, and a facility design that can be sited in geographic locations where mechanical chilling would otherwise be prohibitively expensive. DSX Flex grid demand-response capability is a grid-responsive power management layer that allows an AI factory to participate in demand-response programs, potentially turning compute infrastructure into a grid asset rather than a pure load. DSX Sim AI factory digital twin is a digital twin tool that lets operators model an AI factory’s thermal, power, and networking behavior before a single GPU is installed — reducing the risk of expensive post-build corrections.

The NVIDIA DSX OEM partner ecosystem of OEMs already shipping DSX-compatible hardware includes Dell, HPE, Lenovo, and Supermicro, alongside ASUS, Foxconn, GIGABYTE, Pegatron, QCT, Wistron, and Wiwynn. NVIDIA DSX cloud deployment partners include CoreWeave, Crusoe, Firmus, IREN, Lambda, Nebius, Nscale, and Yotta.

What the Fourth Layer Means for Where AI Factories Are Built

The architecture Buck will outline tonight — Vera Rubin compute at the rack, Vera CPU eliminating the agent inference bottleneck, DSX managing the factory, and Spectrum-XGS linking the facilities — represents a specific bet about how AI infrastructure will be built over the next decade.

Today, frontier AI training is concentrated in a small number of very large campuses, partly because co-locating GPUs in one building is the only reliable way to keep training jobs coherent. Spectrum-XGS, if widely adopted, inverts that calculus. Operators will be able to build smaller, distributed facilities in locations with cheaper power, more available land, or favorable regulatory frameworks, and stitch them together into a single logical cluster. The energy cost of frontier AI training — one of the most frequently cited objections to continued scaling — becomes more manageable when facility siting can be optimized around renewable energy availability rather than proximity to existing fiber hubs.

The OCP MGX ecosystem partner count of 200-plus partners and 100-plus hardware configurations already certified under OCP’s MGX modular reference architecture give the ecosystem a procurement path to Spectrum-XGS-ready infrastructure that does not require building from scratch. The 800 VDC power architecture that NVIDIA developed jointly with Google and Microsoft — ratified by OCP in August 2026 — is expected to appear across multiple sessions at this week’s summit, and represents a second infrastructure standard designed for the 100-megawatt-plus campuses that scale-across networking makes more viable.

Whether the geographic economics argument holds in production will depend on how well Spectrum-XGS’s congestion control survives the latency variance of real long-haul fiber — a test that lab benchmarks cannot replicate. Buck’s keynote, and NVIDIA’s broader presence across breakout sessions running Monday through Thursday, will be the first opportunity for the open hardware community to interrogate those claims with production context rather than specification sheets.

Frequently Asked Questions

How does Spectrum-XGS technically differ from NVIDIA’s existing Spectrum-X Ethernet platform?

Spectrum-X, NVIDIA’s existing AI-optimized Ethernet platform, addresses the Spectrum-X scale-out AI networking tier: connecting GPUs within one data center facility with low-latency, high-bandwidth switching optimized for AI traffic patterns. The Spectrum-XGS versus Spectrum-X overview makes clear that Spectrum-XGS extends that architecture with a “scale-across” capability — a fourth network layer designed to link multiple geographically separate facilities so their GPU clusters appear as a single logical fabric. The mechanisms that enable this are co-packaged optics for higher bandwidth density on long-haul fiber links, distance-aware congestion control that adapts to heterogeneous inter-site latency, and end-to-end telemetry that maintains a unified view of the full distributed fabric. Without those mechanisms, long-haul latency would make cross-site coordination impractical for tightly coupled training workloads.

If AI factories can now span multiple sites, how does that change where operators will build?

The practical implication is that facility siting decisions shift from “find a single campus with enough power and fiber” to “find multiple locations with cheap power and build a distributed cluster.” Regions with abundant renewable energy — often located far from major fiber hubs — become viable AI factory sites if Spectrum-XGS can bridge the connectivity gap. This also reduces the capital concentration risk of building a single very large campus: distributed builds allow incremental investment and faster permitting in jurisdictions with simpler approval processes. Whether the latency tolerance of real training workloads matches what Spectrum-XGS’s architecture promises is the open engineering question that CoreWeave Oracle Spectrum-XGS deployment will begin to answer.

What is the engineering reason the Vera CPU matters for AI workloads — and why does NVIDIA claim x86 can’t do what it does?

In agentic AI inference — the dominant and growing use case where a model iterates through multiple reasoning steps before producing a final output — roughly 75 percent of compute time is spent in the token-by-token decode phase. The CPU coordinates that decode loop and feeds data to the GPU; if the CPU-to-GPU link is too narrow, the GPU sits idle waiting for data. Standard x86 CPUs are connected to GPUs over PCIe 5.0, which maxes out around 64 GB/s. The Vera CPU agentic workload advantage of NVLink-C2C connection to Rubin GPUs runs at 1.8 TB/s — roughly 28 times faster — which is wide enough that the GPU is no longer waiting on the CPU during decode. The addition of per-thread full-bandwidth access on Vera’s Olympus cores means parallel reasoning chains launched by an agentic system do not starve each other for memory bandwidth, a problem that SMT-based x86 cores can encounter under sustained multi-agent load.

What does DSX MaxLPS’s 45°C coolant inlet temperature mean for AI factory costs in practical terms?

Most data-center liquid cooling systems are designed for coolant inlet temperatures well below 45°C, which means the cooling loop itself requires energy-intensive mechanical chilling to keep the coolant cold enough to absorb GPU heat. The DSX MaxLPS 45°C cooling specification raises that inlet temperature to 45°C, which expands the range of climates and facility configurations where liquid cooling can run without mechanical chillers — reducing both the capital cost of cooling infrastructure and the ongoing energy overhead it imposes. The DSX MaxLPS 40 percent GPU density improvement that NVIDIA attributes to MaxLPS reflects the compounding effect: more GPUs fit within a given power budget because the cooling overhead per GPU falls, and the facilities that can host those GPUs expand to include locations that were previously too warm for conventional cooling to handle efficiently without prohibitive energy cost.