Two French chip companies have signed a formal agreement to test whether a European-designed supercomputer processor and a European-built silicon spin-qubit quantum processor can be integrated into a single hybrid computing system — and to jointly pursue a share of the €119 million (approximately $133 million USD) in European quantum funding whose application window closes in November.

SiPearl, the fabless designer behind the Rhea1 processor — Europe’s first sovereign server CPU — and Quobly, a Grenoble-based startup that fabricates silicon spin qubits on standard commercial semiconductor lines, announced a non-exclusive memorandum of understanding on October 9, 2026 to explore combining their respective hardware into a unified hybrid high-performance computing (HPC) and quantum architecture. The agreement marks the first time a European-designed server CPU and a European-built silicon spin-qubit quantum processor unit have entered a formal integration study — closing a strategic gap that prior European hybrid quantum programs left open by pairing non-European classical hosts with various quantum backends.

What makes the partnership distinctive is not the MoU itself — those are common in a field that runs on announced intentions — but what both companies have accomplished before it was signed: SiPearl’s Rhea1 completed its twelve-week functional bring-up in August, and Quobly demonstrated single-chip gate execution of qubit readout, single-qubit gates, and two-qubit gates on a chip fabricated on STMicroelectronics’ commercial 300mm production line. Both companies now hold hardware that actually works. The feasibility question is not whether each piece functions independently. It is whether they can be made to communicate across one of the most extreme temperature gradients in any engineering context.

Silicon Spin Qubits: Why Quobly’s Approach Is Different

The competing quantum computing architectures — superconducting circuits used by IBM and Google, trapped ions used by IonQ and Quantinuum, photonic approaches, and neutral atoms — each requires either exotic fabrication processes or bespoke manufacturing environments that have no overlap with conventional chip production. Quobly’s silicon spin qubit approach works differently.

Silicon spin qubits encode quantum information in the spin state — up or down — of a single electron trapped in a nanoscale chamber called a quantum dot, defined by electrode gates on a standard transistor structure. The physical substrate is the same silicon used to make conventional microchips; the fabrication tooling is the same 300mm commercial semiconductor equipment already running at STMicroelectronics’ Crolles facility near Grenoble. Quobly’s proprietary QSOI® platform builds those quantum dot arrays on a Fully Depleted Silicon-On-Insulator process and co-integrates cryogenic control electronics on the same die using Very Large-Scale Integration principles — the same architectural technique that packs billions of transistors into a conventional processor.

The substrate uses isotopically purified silicon-28, which strips out the naturally occurring silicon-29 isotope. Silicon-29 has a nuclear spin that creates magnetic noise, shortening the time a qubit holds its quantum state. The silicon-28 enrichment significantly extends coherence times and pushes single-qubit gate fidelities toward the 99.9% threshold associated with fault-tolerant operation.

The commercial implication of this approach is structural: because Quobly’s qubits are manufactured on the same industrial lines already used to produce conventional chips at scale, the company’s cost structure and scalability pathway are tied to decades of semiconductor yield improvement, not to novel cryogenic fab construction. Three independent research teams — at RIKEN, QuTech, and the University of New South Wales — simultaneously demonstrated gate fidelities exceeding 99% in silicon spin qubits, validating the technology class.

How Rhea1 Became Europe’s Most Complex Server Chip

SiPearl’s Rhea1, the other half of the proposed hybrid system, arrived at a different kind of milestone. After a development history that began in 2018 under the European Processor Initiative and ran five years behind its original schedule, Rhea1’s first samples were powered on May 13, 2026. The processor features 80 Arm Neoverse V1 cores, 61 billion transistors, four stacks of HBM2E memory, and four DDR5 interfaces, making it the most complex European server processor ever designed.

Rhea1 is fabricated by TSMC using the N6 process — not in Europe. That distinction is worth holding on to, because it defines both the strength and the limit of what “sovereign” means here. SiPearl’s European contribution is the design: the architectural decisions, the system integration, the specific optimization for HPC workloads, and the absence of external backdoors or kill switches — a feature the company markets explicitly in a geopolitical climate where supply-chain security has become a government priority. What Europe does not yet control is advanced-node semiconductor manufacturing: Arm’s Neoverse V1 cores are British IP (now owned by SoftBank); TSMC is Taiwanese. As industry analysts have noted, Rhea1 is a chip designed in Europe with licensed British architecture and made in Taiwan — which is design sovereignty rather than full supply-chain sovereignty.

That tension is not a reason to dismiss the milestone. Rhea1 is slated to equip the CPU cluster module of JUPITER, Europe’s first exascale supercomputer, currently operated by the Jülich Supercomputing Centre in Germany. A successor, Rhea2, is planned for France’s forthcoming Alice Recoque exascale machine. General availability of Rhea1 is targeted for the end of 2026.

What the Feasibility Study Must Solve: The Millikelvin-to-Ambient Gap

The collaboration will proceed in phases. The first and most technically challenging is a feasibility study assessing how SiPearl’s Rhea1 CPU and Seine reference server can interface with Quobly’s QPU control stack and cryogenic electronics. That word — cryogenic — names the central engineering problem the partnership must address before anything else.

Quobly’s silicon spin qubits must operate at millikelvin temperatures inside a dilution refrigerator: approximately 0.015 kelvin, or roughly -459.94°F (-273.30°C), hundreds of times colder than deep space. Rhea1 operates at standard data-center ambient temperatures, typically 20–40°C (68–104°F). Bridging that temperature gap efficiently — transmitting quantum control signals into the refrigerator, reading out quantum results without overwhelming the cooling system with heat from classical electronics, and synchronizing timing between the two worlds at the speed required for hybrid workloads — is an engineering problem that no production system has fully solved at scale. Quobly has developed a cryogenic Process Design Kit specifically to address the classical-quantum interface electronics; the feasibility study will determine whether Rhea1’s architecture and the QSOI® control stack can be coupled within a shared system architecture.

If the feasibility work delivers positive results, the partners plan to move into optimizing and deploying hybrid HPC-quantum workloads, then explore potential architecture synergies for future generations of Quobly’s Alloy product line.

What “Hybrid” Means Right Now — and What It Doesn’t

A note on calibration. All current near-term quantum systems — including Quobly’s Alloy Pioneer, which is expected to become available through the cloud by late 2026 — operate under what physicists call NISQ constraints: Noisy Intermediate-Scale Quantum. The term, coined by physicist John Preskill in 2018, describes quantum devices that have enough qubits to run quantum algorithms but lack the error-correction overhead needed for fault-tolerant computation. In the NISQ regime, every gate operation is susceptible to noise; circuit depth is limited; and for most practically interesting problems, a classical supercomputer still wins.

Quobly’s long-term roadmap targets one million qubits by 2032 — the threshold above which error-corrected, fault-tolerant computation becomes tractable. That goal is technically credible given silicon’s manufacturing density advantage (a million silicon spin qubits could, in principle, fit on a chip the size of a fingernail) but represents a substantial engineering journey. The value of the SiPearl-Quobly feasibility study today lies in establishing interface architecture and integration standards before either company’s hardware reaches fault-tolerant scale — not in delivering immediate quantum advantage over classical HPC.

That framing is consistent with how EuroHPC JU has described its hybrid strategy, which has paired quantum computers using trapped-ion, superconducting, photonic, and neutral-atom technologies with European supercomputing infrastructure since 2022 through programs like HPCQS. The distinction the SiPearl-Quobly effort offers is provenance: for the first time, both the classical CPU and the QPU are European-designed hardware under a single integration roadmap, with joint European funding applications on the horizon.

A Funding Window Both Companies Are Targeting Together

The practical urgency behind the MoU’s timing is visible in the calendar. EuroHPC JU launched six quantum funding calls totaling €119 million on August 13, 2026, with submission deadlines set for November 17, 2026. The calls cover trapped-ion processors, superconducting chiplet QPUs targeting more than 1,000 qubits, neutral-atom platforms, a pan-European quantum testing infrastructure, quantum-key distribution systems, and a pilot-line bridging call linking academic research to Chips JU manufacturing programs — the last of which (HORIZON-JU-EUROHPC-2026-QEXP-14) is explicitly designed to bridge academic quantum research to established semiconductor pilot lines under the Chips JU, directly in Quobly’s lane.

SiPearl and Quobly have stated intent to jointly pursue tenders under the European Chips Joint Undertaking’s quantum programs. Having an all-European CPU-to-QPU integration agreement in place before the November deadline gives both companies a concrete collaborative framework to point to in any joint application — which is at least part of what Thursday’s announcement was designed to accomplish.

Executive Perspectives

Quobly CEO and co-founder Maud Vinet — who spent 20 years at CEA-Leti developing the FD-SOI semiconductor processes that underpin QSOI®, and who holds more than 70 patents in nanotechnology — framed the partnership around the system-level challenge, noting that building scalable quantum computers requires building the classical computing environment around them. Her comments pointed to the interface challenge as a first-class design problem, not an afterthought.

SiPearl CEO and founder Philippe Notton highlighted the pre-existing geographic proximity between the two companies — SiPearl operates an R&D center in Grenoble, the same city where Quobly is headquartered and where STMicroelectronics’ Crolles fabrication facility runs Quobly’s quantum wafers. He described the MoU as a milestone in building a European hardware ecosystem with complementary sovereign solutions across HPC, AI, and quantum computing.

Where European Quantum Stands

The SiPearl-Quobly partnership lands in a broader pattern of European quantum integration activity. In April 2026, Bull — the advanced computing company that builds BullSequana HPC systems, now owned by the French State — signed a similar MoU with Equal1, an Irish silicon-spin quantum company, to integrate Equal1’s rack-mounted silicon-spin quantum servers with Bull’s Qaptiva software stack. That pairing is architecturally similar — silicon spin qubits integrated with HPC infrastructure — but Equal1 is Irish, not French, and its hardware is not designed under the European Processor Initiative.

EuroHPC JU has made European-sourced quantum hardware a policy priority. In February 2026, it deployed Euro-Q-Exa at Leibniz Supercomputing Centre in Munich — a 54-qubit superconducting system developed by IQM Quantum Computers. Six quantum systems across Europe — using trapped-ion, superconducting, photonic, and neutral-atom technologies — are now accessible to European researchers through the EuroHPC quantum access program. None of those deployed systems involves a silicon spin-qubit QPU paired with a European-designed classical CPU under a joint integration roadmap. That gap is what the SiPearl-Quobly MoU is designed to start closing.

Silicon spin qubits remain one of several competing quantum architectures, and none has yet demonstrated fault-tolerant quantum advantage at scale. Quobly’s Alloy Pioneer, when it launches in the cloud later this year, will operate in the NISQ regime alongside everything else. The company’s roadmap toward one million qubits by 2032 is ambitious but technologically coherent, given silicon’s manufacturing density and the progress of the silicon spin qubit field through 2026. What Thursday’s announcement adds is a committed pairing: Europe’s CPU and Europe’s qubit on the same integration roadmap, with a funding window and a thermal gap standing between the agreement and anything deployed.

Frequently Asked Questions

How do silicon spin qubits work, and why are they different from superconducting qubits?

Silicon spin qubits store quantum information in the spin state — up or down — of a single electron trapped in a nanoscale “quantum dot” defined by electrode gates on a silicon transistor. They are fabricated using standard CMOS semiconductor processes, the same kind used to make conventional microchips, which means quantum chips can in principle be produced in existing industrial fabs at scale. Superconducting qubits (used by IBM, Google) require exotic materials cooled to near absolute zero and bespoke manufacturing; they are also roughly one million times larger than a silicon spin qubit, limiting how densely they can be packed. Silicon’s path to scaling — through the same process improvements that have driven conventional chip progress for decades — is the core argument for the approach. Both types still require near-absolute-zero operating temperatures, and neither has yet achieved fault-tolerant quantum advantage at scale.

What is the millikelvin-to-ambient thermal boundary problem, and why is it the central challenge here?

Quobly’s silicon spin qubits must operate inside a dilution refrigerator at approximately 0.015 kelvin — around -459.94°F (-273.30°C), hundreds of times colder than deep space — to preserve quantum coherence. SiPearl’s Rhea1 CPU operates at normal data-center temperatures: roughly 20–40°C (68–104°F). Bridging that temperature gap in a working hybrid system means solving how to send quantum control signals into the refrigerator and extract quantum results without the heat from classical electronics overpowering the cooling system. Timing synchronization between the two units adds a further constraint. No production-scale system has fully solved this interface engineering problem, which is why the SiPearl-Quobly feasibility study — and not an immediate deployment — is what the MoU commits to.

When can researchers actually access Quobly’s quantum computer?

Quobly’s first commercial system, Alloy Pioneer, is expected to become available through the cloud by late 2026 for early adopters in HPC and research environments. Physical deployment within HPC infrastructure — including potential integration with SiPearl’s Seine reference server — is targeted for 2027, subject to the outcome of the feasibility study. The one-million-qubit milestone that would make fault-tolerant quantum computing tractable is on Quobly’s 2032 roadmap.

Does integrating a French-designed CPU with a French quantum chip fully achieve European computing sovereignty?

Not yet. Rhea1 is designed in Europe, but it uses Arm Neoverse V1 cores — British intellectual property now owned by SoftBank — and is manufactured by TSMC in Taiwan. Quobly’s QPU chips are fabricated at STMicroelectronics’ Crolles facility in France, on industrial 300mm FD-SOI lines — a genuinely European manufacturing location. What the SiPearl-Quobly partnership achieves is European design sovereignty and European quantum chip manufacturing, with the classical compute still dependent on non-European IP and foundry capacity. That is a significant but incomplete step toward the full-stack independence that European policymakers describe when they use the term “sovereign.”