The Madhya Pradesh Semiconductor Summit 2026 opened this morning at the Brilliant Convention Centre in Indore with a specific and consequential claim on India’s chip ambitions: a ₹6,200 crore (approximately $655 million) bet on the MP Summit opened in Indore advanced packaging techniques that even India’s operational chip plants in Gujarat have not yet attempted. Chief Minister Dr. Mohan Yadav inaugurated the two-day summit, delivering the keynote address on the theme of Madhya Pradesh’s vision to become a semiconductor hub, but the most significant thing about the summit’s marquee deal is what kind of chip packaging it targets.

Paras Semiconductors — a majority-owned subsidiary of defense engineering company Paras Defence and Space Technologies, incorporated just eight months ago — signed a Memorandum of Understanding with the Madhya Pradesh State Electronics Development Corporation for a proposed ₹6,200 crore ($655 million) greenfield facility on 50 acres in the Indore–Ujjain corridor. The facility is designed specifically for 3D heterogeneous integration and 2.5D/3D advanced IC packaging — the same packaging category that TSMC’s CoWoS process occupies and that every NVIDIA and AMD AI accelerator on the market depends on. India’s current operational OSAT plants in Sanand, Gujarat — run by Micron Technology, Kaynes Semicon, and CG Power — use legacy packaging processes. TechTimes reported in August 2026 that those facilities run on legacy processes and that the harder climb to advanced packaging “is still ahead.”

The Madhya Pradesh summit announced ₹15,800 crore (approximately $1.67 billion) in projected total investment: five projects already granted land in the state totaling ₹10,000 crore (approximately $1.06 billion), with five additional proposals worth ₹5,800 crore (approximately $613 million) currently under government review. More than 50 companies at MP Summit are exhibiting across the two-day event, which runs through October 24.

What 3D and 2.5D IC Packaging Actually Does — and Why India’s Operational Plants Don’t Do It Yet

The difference between what Paras Semiconductors is proposing and what India’s current OSAT plants produce is not a refinement — it is a fundamental architectural shift.

Legacy OSAT, which India’s Sanand facilities currently perform, takes a finished silicon wafer, slices it into individual dies, places each die in a protective package, bonds electrical connections using wire bonding (thin gold, aluminum, or copper wires), and encapsulates the package in epoxy. The resulting chip connects to a circuit board through leads or solder balls. This is the packaging behind QFN, BGA, and SOIC chips — the kind of devices in automotive sensors, consumer electronics, and industrial systems. It is valuable manufacturing. It is not what powers a data center AI accelerator.

An AI accelerator — an NVIDIA H100, an AMD MI300X, any chip doing serious machine learning inference or training — needs to move terabytes of data per second between its logic processors and its memory. Wire bonding cannot do that. The bandwidth is physically constrained by the number of electrical connections a wire-bond package can support.

2.5D packaging solves this with an interposer: a thin slab of silicon, glass, or organic material containing metal wiring at a pitch far finer than anything achievable on a circuit board. Multiple dies — the GPU logic die and four to eight stacks of High-Bandwidth Memory (HBM) — are placed side-by-side on this interposer. Thousands of Through-Silicon Vias (TSVs), tiny metal-filled channels drilled through the silicon, route data between them at bandwidths that wire bonding cannot physically approach. The whole assembly is then packaged as one unified component. This is precisely what TSMC’s CoWoS (Chip on Wafer on Substrate) process does for every major AI chip currently on the market. For a technical primer, see the 2.5D IC interposer packaging overview.

3D packaging goes further: dies are stacked vertically rather than placed side-by-side, with TSVs running through each layer. AMD’s 3D V-Cache, which stacks cache memory directly on processor dies for gaming CPUs, is a commercial example. Heterogeneous integration — combining dies of different process nodes, materials, or functions in one package — is what enables the mixing of logic chips made at TSMC’s leading-edge 4nm node with memory chips made elsewhere, all in one functional assembly.

Both techniques demand precision equipment and engineering expertise categorically different from legacy wire-bonding lines: die-to-wafer bonding systems capable of micron-level alignment, thermal compression bonding equipment, interposer lithography tools, advanced underfill and encapsulation chemistry. Building India’s first serious advanced packaging facility requires importing most of that equipment, just as India’s current operational OSAT plants import their own equipment. For analysis of India’s advanced packaging equipment expertise gap, Business Today’s September 2026 report covers the structural ecosystem challenges in depth.

According to India’s NITI Aayog Frontier Tech Hub, which released its semiconductor roadmap in May 2026, advanced packaging — specifically including 2.5D/3D integration, chiplets, Fan-Out Wafer Level Packaging, and Panel-Level Packaging — is the area where India has identified its clearest near-term opportunity to become a top-three global destination for OSAT by 2035. The global advanced semiconductor packaging market was valued at $20.2 billion in 2024 and is projected to reach $39.6 billion by 2030, according to Grand View Research. The NITI Aayog’s 2035 packaging roadmap positions advanced packaging as India’s national differentiator for semiconductor competitiveness.

Under ISM 2.0, the Union Cabinet explicitly separated incentive levels between legacy and advanced packaging: conventional OSAT receives 25% capex support, while projects targeting 2.5D/3D packaging, wafer-level chip scale packaging, and heterogeneous integration receive 35% capex support. The ISM 2.0 advanced packaging incentives also require applicants for advanced packaging support to already own or possess production-grade licensed technologies for their proposed process — a threshold that Paras Semiconductors, as a company incorporated in February 2026, will need to demonstrate it can clear.

Defense Firm Pivots Into Civilian Chip Packaging — and Explains Why

Paras Defence and Space Technologies, founded in 1996 and listed on India’s NSE and BSE, built its business around high-precision defense products: optics and optronic systems, tactical communication systems, satellite subsystems, radome assemblies, EMP (electromagnetic pulse) protection equipment, and components for missiles, naval platforms, and armored vehicles. Its pivot into semiconductor packaging is deliberate and the rationale is not obscure. Defense systems depend on semiconductor chips. The company’s optics and optronics manufacturing already involves precision engineering, clean environments, and quality systems that overlap with the requirements of semiconductor assembly operations. Paras Semiconductors’ proposed facility will initially focus on semiconductor devices for sensor technologies, optical and optronic systems, and strategic sectors — maintaining the defense customer connection even as it builds capacity for commercial AI chip markets. The Paras Defence defense technology subsidiary history and strategic rationale is detailed in DealStreetAsia’s Reuters-sourced coverage.

The subsidiary was Paras Semiconductors incorporated in February on February 27, 2026. Paras Defence holds a 70% stake. The announced focus — advanced heterogeneous packaging and 3D packaging for AI, high-performance computing, networking, and data center applications — was established from the company’s first regulatory filing. On July 22, 2026, Paras Semiconductors signed the MoU signed on July 22 with the Madhya Pradesh State Electronics Development Corporation for the ₹6,200 crore facility; the state government had already allotted the 50-acre plot in the Indore–Ujjain corridor.

Santosh Kumar, CEO of Paras Semiconductors, stated at the time of the MoU signing that “the next phase of India’s semiconductor growth would depend on building strong manufacturing ecosystems.” Munjal Sharad Shah, Managing Director of Paras Defence, described the project as a milestone in building indigenous semiconductor capabilities. Both statements are detailed in CEO and MD MoU statements from The Machine Maker.

One legitimate open question the announcement leaves unaddressed: Paras Semiconductors has not disclosed which company’s 2.5D/3D technology it holds a production-grade license for, or whether it is developing proprietary processes. The ISM 2.0 technology licensing requirement for the 35% advanced packaging incentive requires that applicants already possess such a license. Without a disclosed technology partner — comparable to Tata Electronics’ partnership with PSMC of Taiwan for its Dholera fab, or CG Power’s partnership with Renesas for its Sanand OSAT — the facility’s path to ISM 2.0 support remains to be confirmed.

Why Madhya Pradesh, Not Gujarat

India’s first wave of operational chip plants concentrated in Sanand, Gujarat — a deliberate clustering strategy that leveraged existing industrial infrastructure and put three facilities in close geographic proximity. Madhya Pradesh is making a different argument: interior India’s land availability, lower real estate costs, the Indore–Ujjain industrial corridor, and the state’s existing strength in electronics manufacturing can compete for the second cluster.

The timing of the Madhya Pradesh Semiconductor Policy 2025 — approved by the State Cabinet in February 2025, ahead of ISM 2.0’s July 2026 approval — matters. The state positioned incentive language before ISM 2.0 was finalized, enabling the MP policy’s provisions to stack on top of central government support. Key state-level incentives under the MP Semiconductor Policy 2025 subsidies: a capital investment subsidy of up to 25% of project cost (or 50% of the central government subsidy, whichever is lower, for nationally approved projects), or 40% for projects not covered by central approval, capped at ₹150 crore (approximately $15.9 million); an interest subsidy of 6% per annum for up to five years, capped at approximately ₹10 crore; land at concessional rates; and a power tariff subsidy of ₹2 per unit (approximately $0.02 per kWh) for the first ten years — significant for semiconductor manufacturing, where electricity costs are a major operating line.

Chief Minister Yadav attended SEMICON India 2026 in New Delhi in September, personally inaugurating the MP Pavilion at Yashobhoomi and meeting representatives from Indian and international semiconductor companies, including a Japanese delegation. He has identified Bhopal and the Indore–Ujjain metropolitan region as the state’s targeted semiconductor hubs, and directed state officials ahead of the summit to prioritize briefing investors on the state’s policy incentives and available land. Details of the CM Yadav at SEMICON India activities and the companies he met are covered in Indian Masterminds’ reporting.

Summit Format: Photonics, Quantum, and the Startup Pipeline

Today’s sessions — the summit’s first day — covered the areas where Madhya Pradesh sees near-term strength: chip packaging and assembly, fabless semiconductor design, and manufacturing supply chains. A panel discussion specifically examined the state as an advanced packaging and testing hub, using the Paras Semiconductors MoU as the concrete anchor. Additional panels addressed building a fabless design ecosystem and semiconductor manufacturing supply chain integration.

Roundtable sessions on Day 1 addressed AI infrastructure requirements for data centers and IP creation in fabless chip design.

Day 2, which will conclude tomorrow with a valedictory ceremony, broadens into more forward-looking technology segments: dedicated sessions are scheduled for artificial intelligence and chip technology, silicon photonics, and quantum technologies — all areas where semiconductor components play foundational roles and where India’s long-term ambitions extend beyond legacy packaging. A session on MSMEs in the semiconductor ecosystem addresses the participation of micro, small, and medium enterprises in the supply chain. The startup competition finale will recognize winners in categories including Semiconductor and Chip Design, Semiconductor Manufacturing and Packaging, Power Electronics and Advanced Materials, Sensors and Photonics, AI and Smart Semiconductor Technologies, IoT and Edge Technologies, and Allied Technologies. IIT Indore’s IITI DRISHTI CPS Foundation served as the Knowledge and Technical Evaluation Partner for the competition. Full summit program and IIT Indore partnership details appear in pre-summit media coverage.

What This Means for India’s Semiconductor Map

India’s national semiconductor roadmap is, as of October 2026, a story with three distinct chapters progressing at different paces. Chapter one — legacy OSAT — is operational, with commercial chip production underway at three Sanand plants. Chapter two — advanced packaging at 2.5D and 3D — has investment commitments but no operational facility yet. Chapter three — leading-edge wafer fabrication — has one project under construction (Tata Electronics at Dholera, Gujarat, targeting first silicon in mid-2028 at the 90nm node) and no commercial production.

The Paras Semiconductors facility, if it reaches commercial operation, would be the opening of chapter two. The national government has put a 35% capex incentive behind it. India’s NITI Aayog has published a roadmap naming top-three global OSAT and advanced packaging status by 2035 as an explicit national target. The gap between intention and operational facility, however, has not narrowed through announcements alone — it narrows through construction timelines, technology partnerships, customer commitments, and equipment installation. The India eyes top-three OSAT slot ambition in Business Today’s coverage of the NITI Aayog roadmap details the scale of that gap.

Business Today’s September 2026 analysis of India’s advanced packaging prospects noted that the segment can give India “a faster route to commercial semiconductor relevance” but cannot give India “a shortcut to semiconductor power” — citing the limited local ecosystem for advanced substrates, materials, equipment, and experienced packaging engineers as the sector’s main structural weakness. Those are not insurmountable gaps. They are the ones that every new India advanced packaging faster route entrant faces, in India and everywhere else.

The Madhya Pradesh summit closes tomorrow, October 24. Whether the ₹15,800 crore (approximately $1.67 billion) in projected investment translates into operational facilities — five projects already granted land moving through construction, five proposals under review converting into signed commitments — will depend on execution, technology partnerships, infrastructure readiness, and ISM 2.0 eligibility confirmations. The specific ambition, however, is now on the table: India’s interior states are competing for the advanced packaging chapter that the Gujarat cluster wrote in legacy terms, and the supply chain segment they’re targeting is the one that determines whether an AI chip can actually ship.

Exchange rate as of October 22, 2026; conversions are approximate.

Frequently Asked Questions

What is 2.5D IC packaging, and how is it different from regular chip packaging?

In conventional OSAT packaging, a single silicon die is enclosed in a protective package with wire bonds connecting its electrical contacts to leads — the kind of packaging in most consumer and industrial chips. In 2.5D packaging, multiple dies are placed side-by-side on a silicon interposer, a thin slab containing high-density metal wiring and Through-Silicon Vias (TSVs). The interposer enables thousands of dense connections between a logic die (such as a GPU) and stacked High-Bandwidth Memory (HBM), delivering terabytes per second of bandwidth that wire bonding physically cannot achieve. Every major AI accelerator — NVIDIA H100, AMD MI300X — uses 2.5D packaging in the form of TSMC’s CoWoS process. India’s existing OSAT plants in Sanand, Gujarat, do not yet perform this type of packaging.

Why is Madhya Pradesh pursuing semiconductor investment now, and what does the state offer?

Madhya Pradesh approved its Semiconductor Policy 2025 in February 2025, ahead of ISM 2.0’s July 2026 approval, establishing a state-level incentive framework that stacks on top of central government capex support. State-specific incentives include up to 40% capital investment subsidy for non-centrally approved projects (capped at ₹150 crore, approximately $15.9 million), a 6% annual interest subsidy for up to five years, land at concessional rates, and a ₹2 per unit power tariff subsidy (approximately $0.02 per kWh) for ten years. Indore is already one of India’s largest industrial cities; the Indore–Ujjain corridor offers land and industrial infrastructure that anchor state ambitions. The state sees itself as a complementary hub to Gujarat’s fab-anchor model — focused on packaging, testing, and design services rather than leading-edge wafer fabrication.

What are the biggest challenges facing India’s push into advanced chip packaging?

India’s near-term structural challenges in advanced packaging fall into four categories: First, technology licensing — ISM 2.0 requires advanced packaging applicants to already own or possess production-grade licensed technologies, a threshold newly incorporated entities like Paras Semiconductors must demonstrate they can meet. Second, the local materials and equipment ecosystem — advanced packaging for AI chips requires precision die-bonding systems, interposer lithography tools, and specialty underfill chemistry, most of which India does not yet manufacture domestically. Third, experienced engineering talent in advanced packaging is scarce globally, not just in India. Fourth, capital intensity — Amkor Technology’s planned advanced packaging campus in Arizona has expanded to $7 billion across two phases; these are not low-cost entry points. ISM 2.0’s 35% capex support for advanced packaging helps close the economics, but India’s packaging entrants will face competition from established hubs in Taiwan, Malaysia, and South Korea with decades of process knowledge.

Does India’s Paras Semiconductors have the technology for 3D heterogeneous integration already?

As of the time of the MoU announcement and this summit, Paras Semiconductors has not publicly disclosed its technology licensing arrangements for 2.5D/3D packaging. The company was incorporated in February 2026 with a stated focus on advanced heterogeneous packaging for AI, HPC, and data center applications. ISM 2.0’s advanced packaging eligibility requires production-grade licensed technology — the same requirement that Tata Electronics fulfilled by partnering with PSMC of Taiwan for its Dholera fab. Whether Paras Semiconductors will announce a comparable technology partner before or during the ISM 2.0 application process remains an open question that will determine the project’s timeline and eligibility for central government support.