A CPU startup founded by the architects behind Apple’s M-series chips disclosed Tuesday that it is building most of its WarpCore processor’s core intellectual property before selecting an instruction set — a reversal of every convention in chip design that is only possible because of a structural property of modern processors that Jim Keller put plainly in 2022: all high-performance CPUs are already running as RISC machines on the inside. Tom’s Hardware reported Nuvacore’s Core First disclosure on September 30, 2026.

Nuvacore — backed by Sequoia Capital and led by Gerard Williams III, John Bruno, and Ram Srinivasan — disclosed the Core First strategy via LinkedIn on September 29. The startup had been publicly silent about its engineering methodology since emerging from stealth in April 2026, saying only that it planned to “rewrite the rules of silicon.”

Why Modern CPUs Are Already ISA-Independent on the Inside

To understand why Core First is credible rather than merely aspirational, it helps to know what happens to an instruction the moment a processor fetches it from memory.

In any modern out-of-order CPU — whether built on x86, Arm, or RISC-V — the first stage is the front-end: a fetch unit, a branch predictor, and an instruction decoder. The decoder is where the ISA lives. For x86, which uses variable-length instructions inherited from decades of accumulation, the decoder is elaborate and expensive: it must parse instruction bytes of varying widths before producing fixed-length internal units the rest of the chip can handle. For Arm and RISC-V, which use fixed-length 32-bit instructions, the decoder is comparatively simple. The ISA reference documentation covers the formal boundaries between ISA and microarchitecture in detail.

Everything that happens after the decoder — register renaming, scheduling, out-of-order execution, branch resolution, retirement — operates entirely on those internal units, called micro-operations or uops. The execution engine has no direct relationship to the ISA. It does not know or care whether the instruction that produced a given uop originally arrived as x86 machine code, an Arm opcode, or a RISC-V instruction. It simply processes data.

Jim Keller — who designed the AMD K7, co-architected the K8, and later oversaw Apple’s CPU cores before joining AMD again to start the Zen project — stated this explicitly in a 2022 talk at the Indian Institute of Science. AMD’s abandoned K12 Arm project failed not because ISA-agnostic design was technically impossible, he said, but because management canceled it. “All modern computers are actually RISC machines inside,” Keller said. “The only blocks you have to change are the decoders.” The Register called K12 cancellation stupid in a June 2022 article reporting Keller’s comments.

Nuvacore’s Core First approach exploits exactly this boundary. The company is developing WarpCore’s execution units, branch-prediction hardware, data paths, caches, and portions of the memory subsystem — the dominant portion of a modern CPU’s design complexity — while leaving the decoder, and thus the ISA commitment, to be decided later. “Rather than beginning with the constraints of an existing architecture and iterating from there, we are starting with the core itself,” the company stated in its LinkedIn disclosure.

AMD Tried This Once, and Canceled It Before It Shipped

Nuvacore’s strategy echoes a chapter from AMD’s history that its leadership — none of whom were at AMD during the episode — would have watched closely.

Under CEOs Rory Read and Lisa Su, AMD spent the middle of the 2010s pursuing what it called “ambidextrous computing”: a plan to serve both x86 and Arm markets from shared processor and platform IP. In 2014, the company announced SkyBridge, a platform that would offer pin-compatible Arm and x86 system-on-chips using shared infrastructure. Separately, Keller was developing K12 — a custom 64-bit Arm core under the ARMv8-A architecture — designed to share microarchitectural DNA with the Zen x86 cores being built in parallel.

Neither product survived. SkyBridge was quietly shelved. K12 never reached production. AMD redirected every available resource toward Zen, which ultimately rescued the company from near-irrelevance, and the Arm cores were canceled once the management structure that had commissioned them changed.

The critical difference between AMD’s attempt and Nuvacore’s approach is structural. AMD was building two parallel ISA implementations simultaneously — K12 for Arm alongside Zen for x86 — and ran out of resources to sustain both. Nuvacore is building one core and keeping the ISA decision genuinely undecided for as long as engineering discipline permits. The two strategies are inverses: AMD tried to execute on two ISAs at once and had to choose; Nuvacore is executing on zero ISAs and will choose once the back-end is mature.

IBM Just Shipped Evidence That This Is Buildable

The strongest contemporary validation for the Core First engineering premise arrived two months before Nuvacore made its disclosure. At Hot Chips 2026 in August, IBM announced the next-generation processor for its Z and LinuxONE mainframe line: a chip that natively executes both IBM’s z/Architecture and Arm’s AArch64 on the same cores, without emulation, without a translation layer, and without separate physical cores for each ISA. TechSpot covered IBM’s dual-ISA 2nm mainframe in detail when the chip was announced.

The processor features 11 cores running above 5.7 GHz on a 2-nanometer process. The Arm ISA support is not implemented as a compatibility shim or a software interpreter — it is built directly into the mainframe core’s own decode logic. IBM’s Christian Jacobi described the ISA-switching overhead as something that “sort of amortizes to zero” when routed through the KVM hypervisor stack, and AIWeekly reported Jacobi on KVM overhead in detail.

IBM’s dual-ISA chip is not an ISA-agnostic chip in Nuvacore’s sense — IBM committed to both ISAs simultaneously and built decoders for both from the start. But it demonstrates, on production silicon at the 2nm node, that the execution back-end of a modern high-performance processor can serve multiple ISAs without fundamental architectural compromise. The back-end is genuinely universal. That is the principle Core First depends on.

What Has Not Been Said

Nuvacore has not disclosed which ISA WarpCore will ultimately implement. It has not announced a manufacturing process node, a core count, a clock target, a power envelope, or a product schedule. Given that ISA selection is still open, many of those details are necessarily undetermined.

The company has framed WarpCore as “a new class of general-purpose CPU designed specifically for the sustained performance and power-efficiency requirements of AI infrastructure and contemporary data centers.” That positions it squarely in the market currently dominated by Nvidia’s Grace CPU (based on Arm’s Neoverse), AMD’s EPYC line, and custom silicon from hyperscalers including Amazon Graviton and Google Axion — all Arm-based, all targeting the same sustained workloads.

As of early 2026, Arm-based machines commanded over 45 percent of server revenues, according to Q1 2026 server market data from IDC reported by Tom’s Hardware, while x86 servers still controlled roughly 52 percent of the market in revenue terms. Intel and AMD together shipped nearly 20 million EPYC and Xeon processors for data center systems in 2025. The ISA landscape is fragmenting: Arm is eating into x86’s server share, and RISC-V is gaining serious traction as SiFive launched SiFive’s rackable RISC-V server — the BigSky SF-2U870, described as the world’s first enterprise-grade rackable 2U RISC-V development server — at Hot Chips 2026 in August 2026.

That fragmentation is precisely what makes ISA-agnostic IP commercially interesting. An Arm licensee could take WarpCore’s underlying microarchitecture and build an Arm implementation. A company exploring RISC-V could commission a RISC-V front-end. An established x86 vendor seeking to refresh its microarchitecture — Intel, under pressure to find new core design talent — could potentially acquire or license the underlying design and build new x86 cores on top of it.

Nuvacore has said none of these things explicitly. But the optionality is structural to the Core First methodology, whether intentional or not.

Does Core First Work, or Is It a Pitch?

The Nuvia precedent matters to any assessment of Nuvacore’s claims. Williams, Bruno, and Srinivasan built a CPU startup from credibility and engineering reputation, refined its technology, and sold it to a large semiconductor company for approximately $1.4 billion — a company, Qualcomm, that then deployed the resulting cores in Snapdragon X Elite, the chip that demonstrated Arm-based Windows laptops could genuinely rival x86 machines in performance. Converge Digest documented Nuvia’s $1.4 billion acquisition and the team’s return with Nuvacore. The team’s track record of building high-performance CPU cores from scratch and seeing them through to commercially successful silicon is real.

SemiAccurate’s assessment of the Nuvia/Oryon cores was blunt: “among the best of their time, no question there.”

The engineering argument for Core First is also genuine. The ISA/microarchitecture boundary is not a convenient fiction Nuvacore invented — it is a documented structural property of every major modern CPU. Keller’s comment about the decoders was not a speculative claim; it was an experienced architect describing what his teams had already discovered while planning Zen. The Nuvia-to-Qualcomm-to-Snapdragon lineage is proof that this team knows how to translate microarchitecture research into shipping silicon.

What Core First cannot yet prove is that deliberate ISA deferral — as opposed to eventual ISA selection — produces a measurably better microarchitecture. It is possible that the most important design decisions, including cache sizing, pipeline width, and memory ordering semantics, benefit from knowing the ISA’s constraints earlier rather than later. The front-end logic required to handle x86 instructions is complex enough that it propagates structural requirements upstream into pipeline design; designing in ignorance of that requirement might produce a back-end that requires later revision when the decoder finally arrives.

That is the honest uncertainty at the center of Core First. Whether it is a revolutionary engineering methodology or an elegant structure for maximizing a startup’s acquisition surface — or both, simultaneously — only WarpCore’s eventual specification will tell.

Did ISA Choice Ever Really Constrain the Best Cores?

The Apple A-series and M-series chips — designed by Williams’ team at Apple — were all Arm-based from the start. Those chips were not architecturally constrained by the Arm ISA; they outperformed x86 competitors across nearly every efficiency metric for years. The ISA was not the bottleneck. The microarchitecture was the advantage.

That history cuts both ways. It suggests that choosing Arm early did not prevent the M1 from being extraordinary — which challenges the Core First framing that ISA-first design is inherently constraining. But it also suggests that Williams knows from direct experience how to build exceptional microarchitectures that happen to have ISA-specific front-ends attached to them — which gives credibility to the claim that he can build the back-end first and attach the front-end later.

What is clear is that WarpCore will eventually need a decoder, and that decoder will tie the chip to whatever ISA Nuvacore selects. The bet Core First is placing is that the best possible back-end is one designed without that constraint — and that when the constraint finally arrives, the IP it attaches to will be valuable enough to attract a customer, a partner, or an acquirer regardless of which ISA it chose.

Frequently Asked Questions

What is the difference between an ISA and a microarchitecture, and why does it matter for WarpCore?

An instruction set architecture (ISA) is the contract between software and hardware — it defines which instructions a processor can execute, how registers are named, and how memory is addressed. Intel’s x86, Arm’s AArch64, and the open-source RISC-V are the three dominant ISAs for high-performance computing. The microarchitecture is the specific circuit-level implementation that fulfills that contract: the pipeline depth, execution unit configuration, branch predictor design, and cache hierarchy. Two processors can implement the same ISA with completely different microarchitectures and produce very different performance characteristics — AMD’s Zen 4 and Intel’s Raptor Lake are both x86, but their internal designs bear almost no resemblance. What Nuvacore calls “Core First” is the recognition that the microarchitecture — not the ISA — is where most of the design work, and most of the performance, lives. The ISA-specific piece is largely confined to the instruction decoder, which sits at the front of the pipeline. By building the back-end first and deferring the decoder, Nuvacore is betting it can optimize the part that matters most before it is constrained by the part that matters least.

Did AMD try something like this before, and what happened?

AMD announced a strategy it called “ambidextrous computing” in 2014, which involved building both x86 and Arm processors from shared IP. The Arm project was codenamed K12 and was being developed alongside the Zen x86 core under architect Jim Keller. The companion platform, SkyBridge, would have offered pin-compatible x86 and Arm chips for the same motherboard. Neither shipped. After Keller departed AMD in 2016, the K12 project was canceled, and AMD directed all resources toward Zen — which ultimately saved the company. Keller later called the cancellation “stupid,” arguing that the shared RISC internal architecture of modern processors made ISA-switching technically straightforward. Nuvacore’s approach is different from AMD’s in one important respect: AMD was building two parallel ISA implementations simultaneously. Nuvacore is building one back-end without committing to any ISA, which is a more deliberate deferral rather than a hedged dual-execution bet.

Which ISA will Nuvacore ultimately choose for WarpCore?

Nuvacore has not disclosed its ISA selection and has stated only that it will choose whichever ISA “works best for the systems that it and its partners plan to build.” The three candidates that observers have noted are Arm (which Williams’ team has built exceptional cores around before), RISC-V (which is rapidly gaining traction among data center startups and avoids licensing fees to Arm Holdings), and x86 (which would require licensing from Intel or AMD but would plug directly into the largest existing software ecosystem). The Core First methodology is specifically designed to keep all three options viable for as long as possible. Nuvacore has also left open whether it will sell physical chips or license its IP as a design — a decision Williams has said will depend on what customers want.

How does IBM’s dual-ISA mainframe chip relate to what Nuvacore is building?

IBM’s next-generation mainframe processor — announced at Hot Chips 2026 in August — natively executes both IBM’s z/Architecture and Arm’s AArch64 on the same cores, without emulation. It features 11 cores running above 5.7 GHz on a 2-nanometer process. IBM’s approach is distinct from Nuvacore’s: IBM committed to both ISAs simultaneously and built decoders for both from the start. But it demonstrates on production silicon that the execution back-end of a modern high-performance processor can serve multiple ISAs without fundamental architectural compromise — which is precisely the engineering principle that Core First depends on. If the back-end were so entangled with ISA-specific requirements that multi-ISA execution required fundamental redesign, IBM’s chip would not be possible. The fact that it exists, and that IBM describes the ISA-switching overhead as negligible, is the most direct contemporary confirmation that Keller’s “only the decoders” claim is correct.