Goldman Sachs published its most comprehensive post-IPO supply model for China’s advanced chip ecosystem on August 24, projecting that China’s shortfall in domestic sub-7-nanometer chip supply will narrow from 92% in 2025 to 34% by 2035. The headline number — a 46% compound annual growth rate in advanced domestic wafer production through 2035 — has already rippled through global semiconductor markets. What the coverage of that number has largely missed is what it requires: Semiconductor Manufacturing International Corporation (SMIC), China’s largest foundry, must triple its production yield at the 7nm node from 23% today to 75% by 2035, and do it using manufacturing equipment that the most advanced chipmakers in the world no longer use. That is not an impossible feat. It is, however, an empirically unprecedented one under deep-ultraviolet-only constraints — and it is the load-bearing pillar of Goldman’s entire 2035 projection.

China’s Advanced Chip Supply Model: What Goldman Projected, and What It Assumes

The Goldman Sachs model, reported by the South China Morning Post on August 24, projects that China’s domestic supply of wafers manufactured at 7 nanometers or below will grow nearly three times faster than domestic demand through 2035: a 46% compound annual growth rate for supply versus 17% for demand. By 2035, Goldman estimates domestic advanced-node output will reach 410,000 wafers per month against demand of 619,000 — a residual shortfall of 34%, compared to the current 92% gap in which China produces only about 8 cents’ worth of its own advanced chip requirements for every dollar consumed domestically.

The primary engine of that expansion, in Goldman’s framework, is SMIC’s capacity buildout. Goldman’s model assumes SMIC adds between 30,000 and 50,000 advanced-node wafers of monthly capacity per year from 2026 through 2031, then a further 20,000 wafers per month annually through 2035. Those are tractable numbers — SMIC has been expanding advanced-node capacity aggressively since demonstrating a 7nm-equivalent process for Huawei’s Kirin 9000S in 2023, and state capital has not stopped flowing.

The yield trajectory is where the model becomes genuinely ambitious. Goldman assumes SMIC’s yield at its advanced node rises from an estimated 23% in 2026 to 50% by 2030 and 75% by 2035. For reference, Taiwan Semiconductor Manufacturing Company (TSMC), which began mass-producing 7nm chips in 2018 using extreme ultraviolet lithography (EUV) equipment that China cannot legally purchase, now achieves yields that can exceed 90% depending on chip design and die complexity. SMIC must close approximately 80% of the gap between its current 23% yield and TSMC’s benchmark in nine years — starting from a lower baseline and using manufacturing equipment roughly a generation less capable. Goldman’s 34% shortfall projection only holds if that yield trajectory is realized.

Why Yield Is the Actual Constraint, Not Capital or Capacity

Understanding why yield matters more than capital for the Goldman model’s validity requires understanding what China’s semiconductor manufacturers are doing inside their fabs.

SMIC does not have access to EUV lithography — the extreme-ultraviolet machines produced by Dutch manufacturer ASML that use 13.5-nanometer-wavelength light to print circuit features in a single, precise exposure pass. That access has been blocked since 2019 by Dutch export controls under US pressure, and reinforced by successive rounds of US semiconductor export controls. Instead, SMIC achieves 7nm-equivalent feature sizes using deep ultraviolet multi-patterning — a technique in which 193-nanometer-wavelength light prints each circuit layer not once but two to four times in separate sequential passes, a process called self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP).

Each additional patterning pass introduces compounding risks. Every pass requires the wafer to be repositioned and re-exposed; the tiny positional errors that accumulate across two, three, or four passes — called overlay errors — degrade circuit precision. More passes mean more processing steps, more opportunities for defects, and higher probability that any given chip on a wafer will fail specification. The result is that SMIC’s multi-patterning approach for its 7nm-equivalent node is structurally yield-challenged in a way that TSMC’s EUV-enabled single-pass production is not.

TSMC’s experience is the only benchmark available. The Taiwanese foundry spent roughly four years after its 2018 7nm launch progressively improving yields toward the 90%-plus range it achieves today — and it did so with EUV equipment, substantially better starting conditions, and decades of accumulated process knowledge. Goldman’s model requires SMIC to achieve 75% yield by 2035 at a node where it is currently at 23%, using equipment that makes each improvement harder and more expensive to capture than at TSMC. That is not a reason to dismiss the model — yield does improve with volume and investment — but it is the single most consequential assumption in the entire 2035 projection, and it deserves to be foregrounded rather than embedded in a footnote.

Hanwha Securities, in a separate analysis published this month, computed that even with CXMT’s production ramp included, the global DRAM market’s sufficiency ratio will run at -9.4% in 2026 and -5.6% in 2027 — meaning the global shortage persists even with China’s most aggressive production additions. Without CXMT, the sufficiency ratio would be -15.5% in 2026 and -12% in 2027. CXMT makes the shortage less severe. It does not flip the market.

CXMT’s Role in the Model: Half of China’s DRAM Demand, With Conditions

Within Goldman’s broader supply model, ChangXin Memory Technologies (CXMT) — the Chinese DRAM maker that raised ¥57.92 billion (approximately $8.6 billion) in Asia’s largest IPO of 2026 on the Shanghai STAR Market in late July — is projected to supply 50% of China’s DRAM demand and 40% of its high-bandwidth memory (HBM) demand by 2028. Goldman characterized the IPO itself as marking China’s semiconductor self-sufficiency strategy entering “a full-fledged commercialization phase” rather than a routine capital event.

The commercial foundation for that confidence is real. CXMT is directing ¥29.5 billion (approximately $4.39 billion) of its IPO proceeds across three areas: ¥13 billion (approximately $1.93 billion) for DRAM technology upgrades, ¥9 billion (approximately $1.34 billion) for next-generation research and development, and ¥7.5 billion (approximately $1.12 billion) for manufacturing line upgrades. The company is targeting approximately 350,000 wafer starts per month by the end of 2026, approaching Micron Technology’s total output, ahead of a new Shanghai fab expected to reach volume production in 2027. By 2028, CXMT is targeting roughly 500,000 wafer starts per month. Server DRAM products — a higher-margin, higher-performance category — grew from 8.4% of CXMT’s revenue in 2024 to 26.5% in 2025, reflecting a deliberate move up the product value chain. Signed customer commitments include a five-year server DRAM deal with ByteDance and a separate agreement with Tencent in June.

Morgan Stanley separately projects CXMT’s DRAM production reaching 388,000 wafers per month by 2028, estimating market share growth that would place it firmly in the global top tier by output volume.

The HBM projection — 40% of China’s demand by 2028 — carries the most significant caveat. CXMT’s IPO prospectus contained no dedicated HBM project and no disclosed capital commitment to a near-term HBM build-out; all named expenditures target existing DRAM process upgrades. SemiAnalysis estimates CXMT’s HBM wafer capacity could reach 55,000 wafers per month in 2027 and 100,000 by 2028, but only if government pressure to redirect capacity toward AI chips intensifies and technology milestones are met on schedule. That is a significant conditional. HBM stacks multiple DRAM dies vertically using through-silicon vias — copper pillars drilled through each die’s silicon substrate — and packages the resulting assembly adjacent to an AI accelerator on a silicon interposer. The architecture is less directly dependent on EUV patterning than planar DRAM scaling, making CXMT’s equipment constraint more manageable for HBM than for advancing process nodes. But Samsung and SK Hynix are already in mass production of HBM4 at 16-layer stacking; CXMT has delivered only HBM3 samples for evaluation.

What China’s Domestic DUV Breakthrough Actually Means for the Goldman Model

Goldman’s supply projections assume export controls remain at their current level — not escalating to a ban on servicing already-installed DUV equipment — for the 46% CAGR to hold. That assumption is itself contested.

On the domestic equipment side, China has made its most visible progress to date. Shanghai Aishengna Electronic Technology Group, a state-backed manufacturer that incorporated in August 2023 and is essentially unknown publicly, began production of domestically developed immersion DUV lithography machines in 2026, with approximately five units expected this year and roughly 20 scheduled for 2027 delivery to SMIC, Hua Hong Semiconductor, and CXMT. The company absorbed engineering teams from lithography startup Yuliangsheng — affiliated with Huawei-backed equipment maker SiCarrier — and from established domestic lithography developer SMEE (Shanghai Micro Electronics Equipment).

The scale of this achievement and its limits must be held together. Five units in 2026 represents roughly 4% of the comparable immersion DUV units that ASML expects to ship this year alone. A Reuters source familiar with the program described Aishengna’s machine as requiring further testing and “far from matching Dutch firm’s competing models.” Chinese industry outlet ICSmart questioned whether the tool has achieved the yield stability its proponents claim, citing sources at domestic wafer fabs who had not yet received commercial deliveries. SMEE’s most production-proven tool, the SSA600 series, is qualified for 90nm processes — far from the 7nm-equivalent processes that Goldman’s model requires SMIC to run at steadily improving yields.

CXMT has a separate potential lever. Korean newspaper Hankgyung reported earlier this year that CXMT began pilot production of bonded DRAM at its Hefei facility — an architecture that fabricates the memory cell array and peripheral circuitry on two separate wafers, each patterned at its individually achievable DUV node, then fuses them using wafer-to-wafer hybrid bonding. Because the array and logic sit on separate substrates, the combined device achieves density equivalent to a more advanced single-wafer node without requiring EUV. Samsung is pursuing a similar architecture under its “B1b” project. Korean industry assessments suggest CXMT may be developing this technology faster than its Korean competitors expected — though bonded DRAM remains years from mass production at CXMT.

Does China’s Wider Chip Investment Change the Trajectory?

Goldman forecasts that China’s semiconductor facility investment will grow at a double-digit annual rate through 2030, with the domestic share of wafer equipment market rising from 26% in 2025 to 38% by 2028. That growing domestic equipment base is the infrastructure layer that would need to exist for Goldman’s yield improvement assumptions to be credible.

China’s overall semiconductor self-sufficiency rate by production volume has already risen from approximately 38% in 2010 to roughly 70% as of June 2026. The 10-percentage-point gap between that 70% volume figure and the residual 34% shortfall in advanced-node production specifically is the clearest expression of where China remains most exposed: not in overall chip production, but in the specific high-complexity, high-performance nodes that AI accelerators and cutting-edge logic chips require.

The wafer equipment market alone is forecast to reach $53 billion (Goldman estimate) next year, with domestic Chinese suppliers capturing a rising share. That rising domestic share is what would eventually allow SMIC to maintain and service its DUV tool base if the MATCH Act — which would ban ASML from servicing existing installed equipment in Chinese fabs — were to become law. The MATCH Act passed the House Foreign Affairs Committee on April 22, 2026; it has not yet been enacted.

What the Goldman Forecast Cannot Change: State Obligations and the Structural Data Risk

Goldman’s supply model is a manufacturing and engineering forecast. It does not change the legal framework under which CXMT and SMIC operate.

China’s National Intelligence Law, enacted in 2017, requires all organizations and citizens under its jurisdiction to support, assist, and cooperate with national intelligence work under Article 7 with no opt-out, with no opt-out mechanism available to private or public companies under Article 14. China’s Cybersecurity Law (2016, with amendments effective January 1, 2026) and Data Security Law (2021) impose additional data localization and government-access requirements. For enterprise buyers evaluating CXMT memory, these obligations arrive alongside the chips and do not disappear if Goldman’s supply model proves accurate. State-linked shareholders held approximately 36% of CXMT’s equity before the IPO, a share that reflects the company’s origin as a state-directed industrial project rather than a commercially independent firm.

For US government contractors: the Department of Defense’s direct procurement ban on CXMT-listed entities took effect June 30, 2026, and is already in force. Section 5949 of the FY2023 National Defense Authorization Act will extend the prohibition to all federal agencies, barring procurement of any semiconductor product from CXMT, its subsidiaries, affiliates, and successors beginning December 23, 2027. An indirect procurement ban covering CXMT components embedded in end-products will take effect for the DoD on June 30, 2027.

Goldman’s forecast is important. It is also a 10-year model built on yield assumptions that have no documented precedent under DUV-only manufacturing constraints, and it does not alter the legal conditions that govern where CXMT’s products can go in the meantime.

The practical summary for buyers, investors, and supply-chain planners: Goldman’s model documents a genuine and accelerating compression of China’s advanced chip shortfall. Whether it reaches 34% by 2035 or settles closer to 50% depends on a specific engineering question — whether SMIC can triple its yield rate using equipment that remains a generation less capable than what TSMC uses — and on a geopolitical question: whether export controls remain at current levels or escalate to DUV servicing restrictions. Neither question has a settled answer. The supply gap is narrowing. The lithography ceiling has not moved.

Frequently Asked Questions

What does Goldman Sachs’ 34% figure actually mean for US chip companies?

It means China will still depend on foreign advanced chips for roughly a third of its domestic demand by 2035 — if Goldman’s yield assumptions hold. That residual dependence keeps Samsung, SK Hynix, Micron, and TSMC relevant for advanced AI and high-performance computing supply into the next decade. But the trajectory from 92% shortfall to 34% is steep enough that global memory pricing, long dominated by a three-company oligopoly, will increasingly have to account for Chinese domestic capacity absorbing demand that would otherwise flow to incumbents. US chipmakers will benefit from the residual gap; they will face growing pricing pressure in commodity DRAM and standard server memory as China self-supplies a rising share of those markets.

Why does SMIC’s yield rate matter more than how many fabs China builds?

Capacity without yield is not competitive production — it is expensive scrap. At a 23% yield, SMIC fabricates fewer than one usable advanced chip for every four wafer slots it runs. At Goldman’s target of 75% yield by 2035, that ratio inverts: three out of four wafer slots produce good chips, making each wafer dramatically more economical to run. The 46% CAGR in China’s advanced-node supply is only achievable if both capacity additions and yield improvements proceed on Goldman’s schedule. Capacity additions alone, with yields flat, would produce far less usable output than the model implies. Yield improvement is where the model’s credibility or fragility lives.

Can CXMT actually supply 40% of China’s high-bandwidth memory demand by 2028?

Goldman’s model projects it can, but the 40% HBM figure is the projection with the most conditions attached. CXMT’s IPO prospectus included no dedicated HBM capital commitment; all named expenditures target existing DRAM process upgrades. SemiAnalysis estimates the HBM capacity trajectory is achievable by 2028 only if government pressure to redirect CXMT’s capacity toward AI chips intensifies significantly and on schedule. As of mid-2026, fewer than 2% of CXMT’s monthly wafer starts produce HBM — a baseline from which reaching 40% of China’s HBM demand in two years would require a dramatic reallocation. Samsung and SK Hynix, the HBM market leaders, are already in mass production of HBM4; CXMT has delivered HBM3 samples for evaluation.

What does China’s National Intelligence Law mean for companies that buy CXMT chips?

China’s National Intelligence Law (2017), Article 7, requires all organizations and citizens under PRC jurisdiction to support, assist, and cooperate with national intelligence work — with no corporate opt-out mechanism under Article 14. This is a fixed legal condition of sourcing from CXMT, not a risk that can be mitigated through contract language or Western subsidiary structures. For B2B enterprise buyers, the primary exposure is not in the chips themselves (DRAM modules do not independently transmit data) but in CXMT’s corporate systems, manufacturing information, and supply chain visibility that state-linked shareholders and intelligence agencies may request access to. Any enterprise with US government contract obligations should consult counsel before making CXMT a primary or significant secondary DRAM source, given the compliance deadlines now in effect and approaching.