Britain’s semiconductor and electronics sector unified under one roof in London this morning for the first time in its history — and the timing is not coincidental. The TechWorks Semiconductors to Systems Summit 2026 (S2S26) opened its plenary at 08:45 BST at Novotel London West in Hammersmith, bringing NMI, DESN, AESIN, and the IoT Security Foundation together for a single day that the UK’s four historically separate deep-tech communities have never managed before. The summit’s 600-plus leaders, 300-plus companies, and delegations from five countries are convening at the exact moment the UK government’s £1.1 billion (approximately $1.5 billion USD) AI Hardware Plan — published by the Department for Science, Innovation and Technology (DSIT) on June 8, 2026 — is moving from a policy document into an operational industrial commitment. The plan is available in full via the UK AI Hardware Plan on gov.uk.

That alignment is not ceremonial. Richard Duffy, Head of Sector Growth in DSIT’s Semiconductor Unit and co-author of both the UK’s National Semiconductor Strategy (2023) and the UK AI Hardware Plan, is speaking in the Scale track’s closing session today. His presence — alongside Hannah Boardman, DSIT’s Director of Frontier and Early-Stage Technologies — signals that S2S26 is functioning as the first formal industry-level test of whether the sector can absorb and act on a £1.1 billion ($1.5 billion USD) commitment that spans £150 million (approximately $204 million USD) in an Advance Market Commitment for novel inference chips, £250 million (approximately $341 million USD) in hardware procurement, and an £80 million (approximately $109 million USD) skills package including a £48 million ($65 million USD) semiconductor skills program scaling undergraduate bursaries from 300 this year to 500 by 2027–28. The details are confirmed in techUK’s analysis of the plan.

The UK dedicated semiconductor sector generated £10.3 billion (approximately $14.03 billion USD) in revenues and employed approximately 16,350 people in 2024/25 — up 7% year-on-year — according to DSIT’s Semiconductor Sector Study 2026. Yet the same study projects a cumulative workforce shortfall of up to 10,460 semiconductor workers by 2030 unless the skills pipeline expands substantially, a finding also confirmed by the DSIT semiconductor workforce study. S2S26 arrives as an ecosystem that is growing but is structurally understaffed — precisely the juncture at which convening all four communities under one program makes industrial sense rather than just symbolic sense.

What S2S26 Actually Is — and Why the Structure Matters

TechWorks is the UK’s principal trade association spanning NMI (National Microelectronics Institute, covering materials and manufacturing), DESN (Design Engineering and Systems Network), AESIN (Automotive Electronics and Systems Innovation Network), and the IoT Security Foundation. For 30 years since TechWorks’ founding, each community has run its annual conference separately. S2S26 is the first time all four communities have deliberately shared a venue, a plenary, and a program — a structural bet that the UK’s semiconductor-to-systems value chain operates as a single interconnected system, and that the artificial boundaries between chip fabrication, systems integration, cybersecurity, and investment have been making the UK’s collective voice smaller than it needs to be.

The four parallel tracks — Build (materials and manufacturing, hosted by NMI), Create (systems integration and verification, hosted by AESIN and DESN), Scale (investment and international partnerships, hosted by the UK Semiconductor Centre), and Secure (cyber resilience and quantum safety, hosted by IoTSF) — are designed to represent distinct layers of that value chain while sharing a day. A compound semiconductor researcher in the Build track and a post-quantum cryptography architect in the Secure track rarely end up in the same room at the same time. Today they will.

The summit is delivered in partnership with the UK Semiconductor Centre (UKSC), the government-backed coordination hub whose CEO Andy McLean has publicly stated that the sector is “already seeing substantial private investment in UK semiconductor companies operating at the forefront of these technologies” and that the UK AI Hardware Plan marks a welcome move toward a “coherent, system-level strategy.” Full details on the day’s program are available via the official TechWorks S2S26 page.

The opening plenary, attended by delegates across all four tracks simultaneously, featured Paul Williamson, Senior Vice President of Corporate Ventures at Arm — whose investment portfolio includes a strategic position in London photonic AI chip startup Olix — alongside Hannah Boardman (DSIT), Charles Sturman (TechWorks CEO), and Jillian Hughes, Founder of Women in TechWorks.

Build Track: UK Materials Sovereignty and the Wide Bandgap Bet

The Build track, anchored by NMI and sponsored by VAT Group and Carl Zeiss, addresses the foundational layer that prior TechWorks events have always treated as a specialist sideshow: the actual materials and process engineering that determines what UK chips can do and what they cannot.

The morning session opened with Caroline O’Brien, CEO of the Compound Semiconductor Applications (CSA) Catapult — the government-backed body whose South Wales cluster represents the UK’s most concentrated sovereign manufacturing capability in compound semiconductors. Compound semiconductors — materials like gallium nitride (GaN), silicon carbide (SiC), and indium phosphide (InP) made from two or more elements rather than pure silicon — can do things silicon cannot: emit light efficiently, switch at high voltages and temperatures, and operate at radio frequencies that silicon struggles to reach. They underpin EV power electronics, photonic AI interconnects, 5G base stations, and defense RF systems. The UK has invested close to £750 million in compound semiconductor R&D since 2000 under the framework of the National Semiconductor Strategy 2023.

The REWIRE program, presented by Katie Hore (Innovation Director) and Professor Peter Gammon (University of Warwick), targets the commercialization gap that has historically trapped UK materials research in the lab. REWIRE focuses on ultra-wide bandgap power semiconductors — materials like gallium oxide and aluminum nitride with bandgaps above 4 electron volts, enabling power device operation at voltages that would destroy conventional silicon or even standard GaN.

Cambridge GaN Devices’ ICeGaN platform, presented by Senior Director Daniel Murphy, illustrates how that commercialization is moving. GaN power devices fabricated on silicon substrates — rather than on more expensive native GaN or SiC substrates — enable cost-competitive manufacturing at commercial scale for industrial and automotive power applications. The platform’s relevance to the AI data center market, where power conversion efficiency directly determines operating costs, is not incidental.

Professor Jon Heffernan, Director of the University of Sheffield and the EPSRC National Epitaxy Facility, addressed photonics materials. Heffernan — who spent 18 years in industrial R&D with Sharp before joining Sheffield and was elected Fellow of the Royal Academy of Engineering in 2025 — oversees a national facility that is the backbone of UK compound semiconductor research. His presence connects academic materials research directly to what IQE plc and Lumentum are attempting to manufacture at scale.

On manufacturing sustainability, Dr. Feras Alkhalil from Pragmatic Semiconductor presented how the company’s FlexIC technology, fabricated at lower temperatures than conventional silicon processes, cuts energy and water consumption substantially — a competitive angle that will matter more as data center operators face pressure on scope 3 emissions.

The Build track’s afternoon session on advanced packaging addressed heterogeneous chiplet integration — the architectural response to Moore’s Law slowdown. Rather than squeezing more transistors onto a single die, chiplet architectures combine multiple specialized dies into a single package using advanced interconnects. John Boston, Managing Director of Custom Interconnect Limited (CIL), noted that CIL’s BP2 facility opened in 2023 is now the UK’s largest OSAT (outsourced semiconductor assembly and test) facility — a direct sovereign capability in a part of the supply chain the UK has historically outsourced. Cadence’s Derek McAulay presented AI-assisted design automation for chiplet systems supporting Arm CSA, OCP FCSA, and UCIe standards — the standards frameworks that will determine whether UK-designed chiplets can be assembled with dies from foundries in Japan, Taiwan, or the EU.

Create Track: Software-Defined Systems and the AI Vehicle

The Create track, hosted by AESIN and DESN with NXP as gold sponsor, focuses on the systems layer where hardware and software converge — and where the automotive sector’s shift toward software-defined vehicles is forcing a rethink of how electronic systems are designed, verified, and secured.

Ian Constance, CEO of the Advanced Propulsion Centre UK and Zenzic, keynoted on software-defined vehicles (SDVs). Constance has overseen more than £1.6 billion (approximately $2.18 billion USD) in zero and low-carbon automotive innovation during his tenure at APC. The SDV transition — replacing dozens of discrete electronic control units with a handful of high-performance compute platforms running software-defined functions — compresses the entire automotive electronics supply chain. A vehicle that once required 70 ECUs from 40 suppliers now runs equivalent functions on three HPCs, with the complexity migrating from hardware to software.

Robert Moran, SVP and General Manager of Automotive Processors at NXP, introduced the concept of a “Neural Axis” — a three-layer distributed intelligence architecture for autonomous systems spanning reasoning, coordination, and reflex layers, modeled loosely on biological nervous systems. The implication for semiconductor design is that automotive silicon must simultaneously handle high-latency strategic reasoning (cloud or edge inference), medium-latency coordination (local sensor fusion), and near-zero-latency reflex responses (safety-critical actuator control) — a requirement profile that no single chip architecture satisfies efficiently.

Tim Mamtora, COO of Raspberry Pi — who joined in March 2026 from Imagination Technologies, where he was chief architect of the RP1 I/O controller that powers the Raspberry Pi 5 — addressed how silicon-in-context design must consider the entire system boundary, not just the chip. The session by Asi Sapir (Synopsys) presented specific performance data for AI-assisted EDA: a multi-agent design automation system achieving 35% higher accuracy and 60% lower latency in RTL-to-signoff tasks compared to human-directed workflows.

Professor Douglas Paul, University of Glasgow and chair of the UK Hub for Quantum Enabled Positioning, Navigation and Timing (PNT) — who received an OBE in the 2025 New Year’s Honours for quantum technology research — hosted a session on resilient PNT that drew in the Royal Navy (Chester Butterworth) and Amentum (John Brotherhood). Quantum-enhanced PNT is the eventual alternative to GPS for applications where GPS jamming or spoofing is a realistic threat — a scenario that has moved from theoretical to documented across multiple conflict zones since 2022.

Secure Track: Hardware Memory Safety, Post-Quantum Migration, and the CRA Deadline

The Secure track is the most technically concentrated of the four programs, addressing a convergence of regulatory deadlines, standards transitions, and hardware security architectures that will reshape how connected devices are built over the next three years.

The most consequential technical development in this track’s sessions is one many engineers outside the security domain have not yet encountered in a production context: CHERI (Capability Hardware Enhanced RISC Instructions), a hardware security architecture developed at the University of Cambridge and SRI International that adds hardware-enforced memory safety to processor instruction sets. Memory corruption vulnerabilities — buffer overflows, use-after-free bugs, out-of-bounds writes — account for approximately 70% of Microsoft-assigned CVEs, according to Microsoft research on memory safety issues in production software. CHERI eliminates entire classes of these at the hardware level by embedding capability metadata directly into processor registers and enforcing bounds-checking in silicon.

Mike Eftimakis, Founding Director of the CHERI Alliance commercialization body, presented an update on the commercial trajectory of the technology. The CHERI Alliance — whose founding members include Arm, Google, Microsoft, and lowRISC — is now coordinating industrial deployment pathways, moving from academic demonstrations (Arm’s Morello prototype, 2022) toward production silicon. The CHERIoT variant, co-developed by Microsoft and lowRISC, implements CHERI specifically for microcontrollers and IoT-class devices where the memory and power constraints of full CHERI are prohibitive.

Haydn Povey, CEO and co-founder of SCI Semiconductor — who led Arm’s Cortex-M processor family before founding Secure Thingz — presented ICENI, a CHERIoT-based secure microcontroller platform designed to enforce least-privilege and hardware-level compartmentalization across AI and critical infrastructure workloads. The significance is not only technical: lowRISC’s OpenTitan project published its Earl Grey 2 engineering roadmap in July 2026, confirming the integration of CHERIoT into its Ibex processor core alongside NIST’s CNSA 2.0-compatible post-quantum cryptography accelerators — meaning the next generation of open-source hardware root-of-trust silicon will ship with both CHERI memory safety and PQC built in.

Javier Orensanz Martinez, CEO of lowRISC — previously VP and General Manager at Arm for more than eight years — presented on how OpenTitan (security IP) and CHERI (memory safety) can provide commercially ready post-quantum solutions, lowering barriers for UK companies to meet the National Cyber Security Centre’s migration deadlines for critical systems. The NCSC’s post-quantum cryptography guidance sets a three-phase roadmap: discovery and assessment complete by 2028, high-priority system migration by 2031, and full migration across all systems by 2035.

Chris Swan of Atsign gave a candid account of the practical obstacles in achieving crypto-agility and putting PQC systems in place across that timeline — from getting different PQC implementations to interoperate, to hybridizing with existing elliptic curve systems. His presentation reflected what practitioners working on actual PQC deployments consistently report: the timeline is achievable for new systems, but retrofitting PQC onto legacy IoT device fleets with no remote update mechanism is a harder problem than the standards themselves address.

The EU Cyber Resilience Act panel was perhaps the most immediately actionable session in the Secure track for UK manufacturers. Jonathan Marshall of SafeShark presented empirical data from a large corpus of PSTI (Product Security and Telecommunications Infrastructure Act) and RED (Radio Equipment Directive) assessments, identifying the most frequent compliance stumbling blocks. The CRA’s October 2027 compliance deadline applies to all products with digital elements sold in the EU — which includes the overwhelming majority of UK electronics manufacturers whose export markets include Europe.

Mohit Arora, Senior Director of Architecture and Product Security at Synaptics — with 26 years across AMD and NXP — addressed the architectural tradeoffs in deploying PQC on resource-constrained silicon and migration strategies from legacy trust architectures, a problem that directly affects the billions of IoT devices that will need PQC-capable hardware to remain secure after 2030.

Scale Track: Where the Capital Is — and What It Needs

The Scale track, organized by the UK Semiconductor Centre, addressed the question that determines whether the UK’s technical strengths become commercial realities: where is the money, who manages it, and what does it require from UK semiconductor companies?

Stan Boland — co-founder and CEO of Five (autonomous vehicles, acquired by Bosch), previously co-founder of Element 14 (acquired by Broadcom) and Icera (acquired by NVIDIA) — opened the Scale keynote with hard-won lessons from building and exiting semiconductor companies. Since 1999, Boland has raised $330 million (approximately £242 million) in venture capital and sold the resulting companies for approximately $1.3 billion (approximately £955 million). His central thesis: the UK consistently produces world-class semiconductor IP and then exports its commercialization to the US. The question S2S26’s Scale track is trying to answer is whether the UK AI Hardware Plan’s £150 million (approximately $204 million USD) Advance Market Commitment — using government procurement to de-risk the jump from prototype to production — can change that dynamic.

Maxime Mallet, General Partner at Jolt Capital — a European semiconductor-specialist venture fund — and Lee Thornton, Partner at IP Group, provided the investor perspective. Thornton, whose portfolio includes Lumai (optical inference), Intrinsic Semiconductor Technologies (non-volatile AI memory), and Quantum Dice (quantum random number generation), holds a DPhil from Oxford in physical chemistry and worked at UK MoD laser facilities before moving to venture. His presence signals that the UK deep-tech investor base is growing more technically literate on semiconductor specifics, not just on software-first business models.

Ekaterina Almasque, Founding Partner of BlankPage Capital and previously General Partner at OpenOcean VC and Managing Director at Samsung Catalyst Fund, brings the cross-border investor perspective. Her track record includes Graphcore — the Bristol AI chip company acquired by SoftBank — and IQM Quantum Computers. The parallel between Graphcore’s trajectory and the UK AI Hardware Plan’s explicit goal of preventing UK-designed technologies from being “commercialised elsewhere” is not lost on anyone in the Scale track audience.

The international partnership session confirmed that S2S26 is drawing genuinely new bilateral engagement. Canada’s Semiconductor Council is attending with a formal delegation for the first time — the first time the council has sent a delegation to a UK semiconductor event — with Paul Slaby (Managing Director) on the panel alongside Sayaka Tomihara (Counsellor, Embassy of Japan), Ivan Stojanovic (representing ChipNL, the Dutch national semiconductor acceleration program), and Andreas Lippert (Saxony Trade & Invest Corp, representing Germany’s Saxony semiconductor cluster).

Richard Duffy (DSIT) presented on the UK’s place in the global semiconductor value chain — specifically on the sectors where the UK can add most value given that the National Semiconductor Strategy has explicitly ruled out competing with Taiwan, South Korea, and the US on leading-edge silicon fabrication at volume. The strategy identifies design, compound semiconductors, and advanced packaging as the UK’s defensible positions — exactly the three areas that the Build, Create, and Scale tracks spent the day examining.

What Hardware Security Means When the Law Requires It

How Post-Quantum Cryptography Actually Works on Constrained Hardware

To understand why the NCSC’s migration timelines matter beyond government communications, it helps to understand the specific vulnerability that post-quantum cryptography addresses. Current public-key cryptography — RSA, elliptic curve Diffie-Hellman, and their variants — derives its security from the computational difficulty of factoring large numbers or computing discrete logarithms. A sufficiently powerful quantum computer running Shor’s algorithm can solve both problems exponentially faster than any classical computer. NIST’s finalized PQC standards — ML-KEM (formerly CRYSTALS-Kyber), ML-DSA (formerly CRYSTALS-Dilithium), FN-DSA (formerly FALCON), and SLH-DSA (formerly SPHINCS+) — are designed to resist exactly those attacks.

The challenge for IoT hardware is that PQC algorithms require significantly more memory and computation than the ECC algorithms they replace. A Cortex-M0+ microcontroller with 32 KB of RAM — the class of device that runs in billions of deployed IoT sensors, smart meters, and industrial controllers — struggles to run ML-KEM key generation in acceptable time while also performing its primary function. Adam McKeown, CTO of Eclypses — with 25 years of security leadership including European banking and UK MoD — addressed how NIST’s new standards and NCSC roadmaps translate into practical data protection strategies for exactly this class of constrained device.

The COSMIC project — announced by lowRISC in November 2025 and backed by DSIT and Innovate UK, targeting March 2028 completion — aims to deliver the world’s first open-source, commercial-quality, CHERI-enabled 64-bit application-class Secure Enclave design: a hardware platform that combines CHERI memory safety with PQC-compatible cryptographic acceleration in a single open design that any UK semiconductor company can license and integrate. If successful, it will be the most significant piece of open-source silicon infrastructure the UK has produced since Cambridge’s original CHERI architecture.

What Does This Look Like for the UK’s Defense and Automotive Supply Chains?

The UK’s semiconductor challenges do not exist in isolation from its defense and automotive industries. Edwin Herrera Alarcón of Leonardo Helicopters presented work on the Proteus autonomous helicopter demonstrator — the UK’s first autonomous full-size rotary-wing aircraft — which requires a new class of safety-certified embedded computing that does not yet have a clear supply chain within the UK. The functional safety panel, moderated by Dr. David Ward (HORIBA MIRA) with Antonio Priore (Imagination Technologies), addressed how complex, connected, autonomous systems can satisfy ISO 26262 and IEC 61508 requirements when the underlying hardware is changing faster than safety standards bodies can certify it.

The V2G session addressed a topic that connects the EV industry directly to the power semiconductor specialists in the Build track. Paolo Bargiacchi, Director of Product and Strategy at Motion Applied (formerly McLaren Applied), presented power electronics developed for Formula E and Le Mans Hypercar racing now being translated into bidirectional charger hardware for road vehicles and maritime applications. The underlying semiconductor technology — SiC devices switching at 100 kHz and above, fabricated by companies like Vishay (whose SiC specialist Praneet Bhatnagar holds a PhD from Newcastle University in SiC devices) — determines whether V2G can deliver its theoretical grid-stabilization benefits at commercial scale.

UK AI Hardware Plan: From £1.1bn Commitment to Industry Execution

The UK AI Hardware Plan’s publication in June 2026 marked the first time the UK government committed to being on the demand side of its own semiconductor strategy, not just the supply side. The plan’s £150 million (approximately $204 million USD) Advance Market Commitment is designed to do what the National Semiconductor Strategy’s upstream R&D funding could not: guarantee a buyer for novel UK-designed chips that have cleared prototype but not yet found commercial volume. The £250 million (approximately $341 million USD) hardware procurement opportunity goes further still, committing government departments as anchor customers for UK-designed AI hardware in a sector where government procurement has historically defaulted to established American and Asian incumbents.

The Chips Coalition — founded by techUK, Global Tech Advocates, and TechWorks — has been the primary channel through which industry shaped the plan’s provisions. S2S26 is the first major convening of that coalition’s constituent companies since the plan’s publication. The gap between what is in the document and what the sector can actually deliver — in timelines, in volume, in the workforce that designs and tests the hardware — is the subtext behind every conversation in the Scale track today.

Evening Reception

All four tracks are scheduled to converge at 18:00 BST (1:00 PM ET) for an evening reception sponsored by IC Resources, with the firm’s founder Neil Dickins hosting. IC Resources, founded in 1999, is a specialist recruiter for the semiconductor sector and has been a long-standing TechWorks partner. The reception is the first time delegates from all four tracks will share a room after separate days of parallel programming — the practical test of whether the cross-value-chain format has produced enough common ground for genuine interdisciplinary conversation.

What Comes Next

S2S26 is a starting point, not a conclusion. The UK Semiconductor Workforce Study projects a cumulative shortfall of up to 10,460 semiconductor engineers by 2030. The UK AI Hardware Plan’s skills package — 500 undergraduate bursaries per year by 2027-28, a new £12 million (approximately $16 million USD) Centre for Doctoral Training in Chip Design, and 500 additional PhD top-up positions via the expanded TechFirst program — addresses the pipeline. Whether the pipeline can be expanded fast enough to staff the design centers, test facilities, and manufacturing operations that the UK’s strategy requires is the question that will determine whether today’s convergence produces lasting industrial capability or a very well-attended conference.

The geopolitical context is not separable from the industrial one. Export controls on indium phosphide substrates from China, the US CHIPS Act’s effect on global foundry capacity, and the EU’s European Chips Act are all reshaping where semiconductor investment goes. The UK’s position — design strength, compound semiconductor manufacturing capability, and now a coherent government strategy — puts it in a genuine position to benefit from supply chain diversification. Whether it takes that position will depend on decisions made in rooms like the ones at Novotel London West today.

Frequently Asked Questions

What is TechWorks S2S26 and why is it significant?

S2S26 — the Semiconductors to Systems Summit 2026 — is TechWorks’ 30th anniversary summit and the first time four of Britain’s leading deep-tech communities (NMI, DESN, AESIN, and the IoT Security Foundation) have met under a single program. Its significance in 2026 specifically is that it is happening at the same moment the UK government’s £1.1 billion (approximately $1.5 billion USD) AI Hardware Plan is being operationalized, with DSIT’s semiconductor strategy authors present at the event. It represents the UK semiconductor ecosystem’s first attempt to present itself as a coherent, cross-value-chain capability to investors, government, and international partners simultaneously.

What is CHERI hardware security and why does it matter for IoT devices?

CHERI (Capability Hardware Enhanced RISC Instructions) is a hardware security architecture developed at the University of Cambridge that adds hardware-enforced memory safety to processor instruction sets. By encoding memory bounds and permissions directly into hardware capabilities (tagged pointers), CHERI prevents entire classes of vulnerabilities — buffer overflows, use-after-free bugs — that account for an estimated 70% of exploited security flaws in production software. The CHERIoT variant targets microcontrollers and IoT-class devices. The EU Cyber Resilience Act (compliance deadline October 2027) and the UK PSTI Act are creating regulatory demand for exactly this kind of hardware-rooted security — making CHERI’s commercial trajectory increasingly tied to compliance timelines rather than purely to market demand.

What does the post-quantum cryptography deadline mean for device makers?

The UK’s National Cyber Security Centre (NCSC) has established a three-phase migration roadmap: organizations should complete cryptographic discovery by 2028, execute high-priority system upgrades by 2031, and achieve full migration to post-quantum cryptography across all systems by 2035. Post-quantum cryptography refers to algorithms designed to resist attacks from quantum computers running Shor’s algorithm, which can break today’s RSA and elliptic-curve encryption. For device manufacturers, this means new hardware must support NIST’s finalized PQC standards (ML-KEM, ML-DSA, FN-DSA, SLH-DSA) and existing IoT device fleets with no remote firmware update path face a hard end-of-security-life. The challenge is running these more computationally intensive algorithms on resource-constrained microcontrollers — the subject of multiple S2S26 Secure track sessions.

How is UK compound semiconductor manufacturing connected to AI data center demand?

UK compound semiconductor companies — IQE (epitaxial wafers), Lumentum (InP photonic chips, Caswell site), Cambridge GaN Devices (power GaN) — supply materials and components that are increasingly critical to AI data center infrastructure. Silicon photonics interconnects, which move data between chips using light rather than copper, require indium phosphide lasers or alternatives (such as the GaAs quantum-dot comb lasers that Quintessent began sampling in August 2026). China’s export controls on InP substrates have created supply chain pressure that directly advantages UK and European compound semiconductor capability. The Build track at S2S26 is examining how that advantage can be converted into commercial scale.